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PCA9509
Level translating I2C-bus/SMBus repeater
Rev. 05 -- 10 July 2009 Product data sheet
1. General description
The PCA9509 is a level translating I2C-bus/SMBus repeater that enables processor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus maximum capacitance of 400 pF on the higher voltage side. Port A allows a voltage range from 1.0 V (as low as 0.95 V in special cases) to VCC(B) - 1.0 V and requires no external pull-up resistors due to the internal current source. Port B allows a voltage range from 3.0 V to 5.5 V and is overvoltage tolerant. Both port A and port B SDA and SCL pins are high-impedance when the PCA9509 is unpowered. The bus port B drivers are compliant with SMBus I/O levels, while port A uses a current sensing mechanism to detect the input or output LOW signal which prevents bus lock-up. Port A uses a 1 mA current source for pull-up and a 200 pull-down driver. This results in a LOW on the port A accommodating smaller voltage swings. The output pull-down on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold of the internal buffer is set about 50 mV lower than that of the output voltage LOW. When the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on the port B drives a hard LOW and the input level is set at 0.3 of SMBus or I2C-bus voltage level which enables port B to connect to any other I2C-bus devices or buffer. The PCA9509 drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the EN pin when the bus is idle.
2. Features
I Bidirectional buffer isolates capacitance and allows 400 pF on port B of the device I Voltage level translation from port A (1 V [0.95 V in special cases] to VCC(B) - 1.0 V) to port B (3.0 V to 5.5 V) I Requires no external pull-up resistors on lower voltage port A I Active HIGH repeater enable input I Open-drain inputs/outputs I Lock-up free operation I Supports arbitration and clock stretching across the repeater I Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters I Powered-off high-impedance I2C-bus pins
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
I Operating supply voltage range of 1.0 V (0.95 V in special cases) to VCC(B) - 1.0 V on port A, 3.0 V to 5.5 V on port B I 5 V tolerant port B SCL, SDA and enable pins I 0 Hz to 400 kHz clock frequency Remark: The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater. I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: TSSOP8, SO8, XQFN8
3. Ordering information
Table 1. Ordering information Package Name SO8 TSSOP8 XQFN8 Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm Version SOT96-1 SOT505-1 SOT902-1 Type number Topside mark PCA9509D PCA9509DP PCA9509GM PCA9509 9509 P9X[1]
[1]
`X' will change based on date code.
4. Functional diagram
VCC(A) VCC(B)
PCA9509
VCC(A)
1 mA
A1 VCC(A)
1 mA
B1
A2
B2
EN
002aac125
GND
Fig 1.
Functional diagram of PCA9509
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
2 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
5. Pinning information
5.1 Pinning
VCC(A) A1 A2 GND
1 2 3 4
002aac126
8 7
VCC(B) B1 B2 EN
VCC(A) A1 A2 GND
1 2
8 7
VCC(B) B1 B2 EN
PCA9509DP
PCA9509D
3 4
002aac127
6 5
6 5
Fig 2.
Pin configuration for TSSOP8
Fig 3.
VCC(B)
Pin configuration for SO8
terminal 1 index area VCC(A) 1
8
7
B1
PCA9509GM
A1 2 6 B2
A2
3 4
5
EN
GND
002aac776
Transparent top view
Fig 4.
Pin configuration for XQFN8
5.2 Pin description
Table 2. Symbol VCC(A) A1[1] A2[1] GND EN B2[1] B1[1] VCC(B)
[1]
Pin description Pin 1 2 3 4 5 6 7 8 Description port A power supply port A (lower voltage side) port A (lower voltage side) ground (0 V) enable input (active HIGH) port B (SMBus/I2C-bus side) port B (SMBus/I2C-bus side) port B power supply
Port A and port B can be used for either SCL or SDA.
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
3 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
6. Functional description
Refer to Figure 1 "Functional diagram of PCA9509". The PCA9509 enables I2C-bus or SMBus translation down to VCC(A) as low as 1.0 V (as low as 0.95 V in special cases) without degradation of system performance. The PCA9509 contains 2 bidirectional open-drain buffers specifically designed to support up-translation/down-translation between the low voltage and 3.3 V SMBus or 5 V I2C-bus. The port B I/Os are over-voltage tolerant to 5.5 V even when the device is unpowered. The PCA9509 includes a power-up circuit that keeps the output drivers turned off until VCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be applied in any sequence at power-up. After power-up and with the EN pin HIGH, a LOW level on port A (below approximately 0.15 V) turns the corresponding port B driver (either SDA or SCL) on and drives port B down to about 0 V. When port A rises above approximately 0.15 V, the port B pull-down driver is turned off and the external pull-up resistor pulls the pin HIGH. When port B falls first and goes below 0.3VCC(B), the port A driver is turned on and port A pulls down to 0.2 V (typical). The port B pull-down is not enabled unless the port A voltage goes below VILc. If the port A low voltage goes below VILc, the port B pull-down driver is enabled until port A rises above approximately 0.15 V (VILc), then port B, if not externally driven LOW, will continue to rise being pulled up by the external pull-up resistor. Remark: Ground offset between the PCA9509 ground and the ground of devices on port A of the PCA9509 must be avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3 mA of current at 0.4 V will have an output resistance of 133 or less (R = E / I). Such a driver will share enough current with the port A output pull-down of the PCA9509 to be seen as a LOW as long as the ground offset is zero. If the ground offset is greater than 0 V, then the driver resistance must be less. Since VILc can be as low as 90 mV at cold temperatures and the low end of the current distribution, the maximum ground offset should not exceed 50 mV. Bus repeaters that use an output offset are not interoperable with the port A of the PCA9509 as their output LOW levels will not be recognized by the PCA9509 as a LOW. If the PCA9509 is placed in an application where the VIL of port A of the PCA9509 does not go below its VILc it will pull port B LOW initially when port A input transitions LOW but the port B will return HIGH, so it will not reproduce the port A input on port B. Such applications should be avoided. Port B is interoperable with all I2C-bus slaves, masters and repeaters.
6.1 Enable
The EN pin is active HIGH and allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up until after the system power-up reset. It should never change state during an I2C-bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus parts being enabled. The enable pin should only change state when the bus and the repeater port are in an idle state to prevent system failures.
PCA9509_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
4 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus). The size of these pull-up resistors depends on the system. Each of the port A I/Os has an internal pull-up current source and does not require the external pull-up resistor. Port B is designed to work with Standard-mode and Fast-mode I2C-bus devices in addition to SMBus devices. Standard-mode I2C-bus devices only specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus system where Standard-mode devices and multiple masters are possible. Under certain conditions higher termination currents can be used.
7. Application design-in information
A typical application is shown in Figure 5. In this example, the CPU is running on a 1.1 V I2C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
1.1 V
3.3 V
10 k
10 k
VCC(A) SDA SCL 1.1 V MASTER CPU
10 k
VCC(B) B1 B2 SDA SCL SLAVE 400 kHz
A1 A2
PCA9509
EN bus A bus B
002aac128
Fig 5.
Typical application
When port B of the PCA9509 is pulled LOW by a driver on the I2C-bus, a CMOS hysteresis detects the falling edge when it goes below 0.3VCC(B) and causes the internal driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the PCA9509 falls, first a comparator detects the falling edge and causes the internal driver on port B to turn on and pull the port B pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 6 and Figure 7. If the bus master in Figure 5 were to write to the slave through the PCA9509, waveforms shown in Figure 6 would be observed on the B bus. This looks like a normal I2C-bus transmission. On the A bus side of the PCA9509, the clock and data lines would have a positive offset from ground equal to the VOL of the PCA9509. After the 8th clock pulse, the data line will be pulled to the VOL of the master device, which is very close to ground in this example. At the end of the acknowledge, the level rises only to the LOW level set by the driver in the PCA9509 for a short delay while the B bus side rises above 0.5VCC(B), then it continues HIGH. It is important to note that any arbitration or clock stretching events require that the LOW level on the A bus side at the input of the PCA9509 (VIL) is below VILc to be recognized by the PCA9509 and then transmitted to the B bus side.
PCA9509_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
5 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
9th clock pulse acknowledge SCL
SDA
002aab644
Fig 6.
Bus B SMBus/I2C-bus waveform
9th clock pulse acknowledge SCL
SDA VOL of PCA9509
VOL of master
002aac129
Fig 7.
Bus A lower voltage waveform
8. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(B) VCC(A) VI/O II/O II Ptot Tstg Tamb Tj Tsp Parameter supply voltage port B supply voltage port A voltage on an input/output pin input/output current input current total power dissipation storage temperature ambient temperature junction temperature solder point temperature 10 s max. operating in free air port A port B; enable pin (EN) Conditions Min -0.5 -0.5 -0.5 -0.5 -65 -40 Max +6.0 +6.0 +6.0 +6.0 20 20 100 +150 +85 +125 300 Unit V V V V mA mA mW C C C C
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
6 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
9. Static characteristics
Table 4. Static characteristics GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VCC(B) VCC(A) ICC(A) ICC(B) VIH VIL VILc VIK ILI IIL VOL supply voltage port B supply voltage port A supply current port A supply current port B HIGH-level input voltage LOW-level input voltage contention LOW-level input voltage input clamping voltage input leakage current LOW-level input current LOW-level output voltage VCC(A) = 0.95 V to 1.2 V VCC(A) = > 1.2 V to (VCC(B) - 1 V) VOL-VILc ILOH Cio VIH VIL VIK ILI IIL VOL ILOH Cio Enable VIL VIH IIL(EN) ILI Ci
[1]
Parameter
Conditions
Min 3.0 1.0[2]
Typ[1] Max 0.45 3.0 0.9 -1.0 0.18 0.2 50 6 0.1 3 2 5.5 VCC(B) - 1 0.9 5 1.1 VCC(A) +0.3 -0.5 1 -0.45 0.25 0.3 10 7 VCC(B) -0.5 +1.0 10 0.2 10 5
Unit V V mA mA mA V V V V A mA V V mV A pF V V A A V A pF
all port A static HIGH all port A static LOW all port B static HIGH port A port A IL = -18 mA VI = VCC(A)
[4] [5] [5] [3] [3]
0.25 1.25 0.5 0.7VCC(A) -0.5 -0.5 -1.5 -1.5 -
Input and output of port A (A1 to A2)
+0.15 -
difference between LOW-level output and LOW-level input voltage contention HIGH-level output leakage current input/output capacitance HIGH-level input voltage LOW-level input voltage input clamping voltage input leakage current LOW-level input current LOW-level output voltage HIGH-level output leakage current input/output capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current on pin EN input leakage current input capacitance VI = 3.0 V or 0 V VI = 0.2 V, EN; VCC = 3.6 V port B port B IL = -18 mA VI = 3.6 V VI = 0.2 V IOL = 6 mA VO = 3.6 V VO = 1.1 V
[6]
Input and output of port B (B1 to B2) 0.7VCC(B) -0.5 -1.5 -1.0 -0.5 0.9VCC(A) -1 -1 +0.3VCC(B) V
+0.1VCC(A) V VCC(B) +1 +1 3 V A A pF
Typical values with VCC(A) = 1.1 V, VCC(B) = 5.0 V.
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
7 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
[2]
If the PCA9509 is not being enabled or disabled, the VCC(A) minimum is 0.95 V with a corresponding decrease in the IIL, which will drop below the minimum specification of -450 A at cold temperature (see Figure 8 and Figure 9). This will not significantly change the rise and fall times of the signals on port A since the IIL value represents the current source pull-up current, so a lower current into the same capacitance will result in a slower rise time and a longer transition time in general, however since the lower current is also associated with a lower voltage swing the delay is somewhat compensated. The key point of the graphs is that the current has a temperature dependence, and the output driver will also have the same temperature dependency so that the output offset of ~200 mV on port A is nearly temperature independent. Even though the IIL parameter indicates that at VCC(A) of 0.95 V the PCA9509 can only sink up to 400 A instead of 450 A at cold temperature, the output is designed to be somewhat resistive such that under nominal conditions (1.1 V) the current source pull-up will source 1 mA and the output pull-down will sink the 1 mA at ~200 mV, so as the current source current decreases the output pull-down resistance increases in order to maintain the offset. VIL specification is for the falling edge seen by the port A input. VILc is for the static LOW levels seen by the port A input resulting in port B output staying LOW. The port A current source has a typical value of about 1 mA, but varies with both VCC(A) and VCC(B). Below VCC(A) of about 0.7 V the port A current source current drops to 0 mA. The current source current dropping across the internal pull-down driver resistance of about 200 defines the VOL. As long as the chip ground is common with the input ground reference the driver resistance may be as large as 120 . However, ground offset will rapidly decrease the maximum allowed driver resistance. Guaranteed by design.
[3] [4]
[5] [6]
0 IIL (mA) -0.4
(1) (2)
002aae733
0 IIL (mA) -0.4
(3) (4) (2)
002aae734
(1)
-0.8
(3)
(4)
-0.8
-1.2
(5)
-1.2
(5)
-1.6 -40
25 Tamb (C)
85
-1.6 -40
25 Tamb (C)
85
Pins under test = An pins (1) High limit (2) Maximum (3) Mean (4) Minimum (5) Low limit
Pins under test = An pins (1) High limit (2) Maximum (3) Mean (4) Minimum (5) Low limit
Fig 8.
LOW-level input current as a function of temperature; VCC(A) = 1.0 V
Fig 9.
LOW-level input current as a function of temperature; VCC(A) = 0.95 V
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
8 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
10. Dynamic characteristics
Table 5. Symbol tPLH tPHL tTLH tTHL tPLH tPLH2 Dynamic characteristics Parameter LOW to HIGH propagation delay HIGH to LOW propagation delay LOW to HIGH output transition time HIGH to LOW output transition time LOW to HIGH propagation delay LOW to HIGH propagation delay 2 Conditions port B to port A port B to port A port A port A port A to port B port A to port B; measured from the 50 % of initial LOW on port A to 1.5 V rising on port B port A to port B port B port B EN HIGH before START condition EN HIGH after STOP condition port B to port A port B to port A port A port A port A to port B port A to port B; measured from the 50 % of initial LOW on port A to 1.5 V rising on port B port A to port B port B port B EN HIGH before START condition EN HIGH after STOP condition
[1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1]
Min 69 63 14 5 -69 91
Typ 109 86 22 8.1 -91 153
Max 216 140 96 16 -139 226
Unit ns ns ns ns ns ns
VCC(A) = 1.1 V; VCC(B) = 3.3 V
tPHL tTLH tTHL tsu th tPLH tPHL tTLH tTHL tPLH tPLH2
HIGH to LOW propagation delay LOW to HIGH output transition time HIGH to LOW output transition time set-up time hold time LOW to HIGH propagation delay HIGH to LOW propagation delay LOW to HIGH output transition time HIGH to LOW output transition time LOW to HIGH propagation delay LOW to HIGH propagation delay 2
[1] [1][2] [1]
73 15 100 100 69 63 14 5 -69 91
122 61 24 105 86 27 8 -89 131
183 40 216 140 96 35 -139 226
ns ns ns ns ns ns ns ns ns ns ns
VCC(A) = 1.9 V; VCC(B) = 5.0 V
tPHL tTLH tTHL tsu th
[1] [2]
HIGH to LOW propagation delay LOW to HIGH output transition time HIGH to LOW output transition time set-up time hold time
[1] [1][2] [1]
73 15 100 100
99 65 31 -
183 40 -
ns ns ns ns ns
Load capacitance = 50 pF; load resistance on port B = 1.35 k. Value is determined by RC time constant of bus line.
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
9 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
10.1 AC waveforms
VCC(B) input 0.5VCC(B) tPHL 70 % 0.5VCC(B) 0.1 V tPLH 70 % VCC(A) output VOL
002aab646
VCC(A) input 0.5VCC(A) tPHL 70 % 0.5VCC(A) tPLH 70 % tTLH
002aab647
VCC(B)
output
0.5VCC(A) 0.5VCC(A) 30 % 30 % tTHL
0.5VCC(B) 0.5VCC(B) 30 % 30 % tTHL
tTLH
Fig 10. Propagation delay and transition times; port B to port A
Fig 11. Propagation delay and transition times; port A to port B
input port A 50 % of initial value
output port B tPLH2
0.5VCC(B)
002aab648
Fig 12. Propagation delay from the port A's external driver switching off to port B LOW-to-HIGH transition; port A to port B
11. Test information
VCC(B) VCC(A) PULSE GENERATOR VI DUT
RT CL
VCC(B)
RL
VO
002aab649
RL = load resistor; 1.35 k on port B CL = load capacitance includes jig and probe capacitance; 50 pF RT = termination resistance should be equal to Zo of pulse generators
Fig 13. Test circuit for open-drain outputs
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
10 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
12. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 14. Package outline SOT96-1 (SO8)
PCA9509_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
11 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 15. Package outline SOT505-1 (TSSOP8)
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Product data sheet
Rev. 05 -- 10 July 2009
12 of 19
NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
SOT902-1
D terminal 1 index area
B
A
E
A A1
detail X
L1 L
e
4
e v M C A B w M C
5
C y1 C y
3
metal area not for soldering
2 6
b
e1
e1
7 1
terminal 1 index area
8
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05
OUTLINE VERSION SOT902-1
REFERENCES IEC --JEDEC MO-255 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-11-25 07-11-14
Fig 16. Package outline SOT902-1 (XQFN8)
PCA9509_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
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NXP Semiconductors
PCA9509
Level translating I2C-bus/SMBus repeater
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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Product data sheet
Rev. 05 -- 10 July 2009
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 17) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6 and 7
Table 6. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 7. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17.
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 17. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 8. Acronym CDM CMOS CPU ESD HBM I/O I2C-bus MM NMOS RC SMBus Abbreviations Description Charged-Device Model Complementary Metal-Oxide Semiconductor Central Processing Unit ElectroStatic Discharge Human Body Model Input/Output Inter-Integrated Circuit bus Machine Model Negative-channel Metal-Oxide Semiconductor Resistor-Capacitor network System Management Bus
PCA9509_5
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Product data sheet
Rev. 05 -- 10 July 2009
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15. Revision history
Table 9. Revision history Release date 20090710 Data sheet status Product data sheet Change notice Supersedes PCA9509_4 Document ID PCA9509_5 Modifications: PCA9509_4 PCA9509_3 PCA9509_2 PCA9509_1
*
Table 4 "Static characteristics", sub-section "Input and output of port A (A1 to A2), symbol VOL is split according to 2 different supply voltage conditions Product data sheet Product data sheet Product data sheet Product data sheet PCA9509_3 PCA9509_2 PCA9509_1 -
20090617 20090611 20070629 20060627
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
17 of 19
NXP Semiconductors
PCA9509
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16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9509_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 10 July 2009
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NXP Semiconductors
PCA9509
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18. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 10.1 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5 Application design-in information . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering of SMD packages . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 July 2009 Document identifier: PCA9509_5

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